In modern integrated-circuit design, embedded memories occupy a large area of the chip. In modern microprocessors, for example, embedded memories often occupy more than 30% of the chip area, and in a system-on-a-chip (SOC), they may occupy more than 60% of the chip area. Indeed, the percentage of chip area occupied by embedded memories in SOCs is expected to rise to 94% in the next decade. Consequently, the yield of embedded memories will likely be determinative of the yield of SOCs.
Embedded memories typically comprise some of the densest physical structures on a chip and have some of the smallest feature sizes. Consequently, memories are usually more sensitive to defects than combinational logic. A common solution for addressing defective memories is to include one or more spare rows and/or columns in the memory array. The spare row and/or columns can be activated if a memory test determines that a standard memory row or column is defective. One memory-testing scheme that can be used to detect defects in a memory is known as built-in self-test (BIST) and involves locating the test-generation and test-analyzing hardware onto the chip itself. BIST schemes typically utilize some type of built-in self-repair analyzer (BISRA) to analyze the failure information detected and to determine how to repair a memory using the available spare rows or spare columns to cover all faulty cells. The repair information determined can then be sent to the on-chip repair logic or to external repair equipment that performs the actual physical repair.
Because the failure information determined by the BIST hardware can be fairly large, it is not practical to store all the information in the BISRA. Accordingly, a typical BISRA has to allocate a spare row or a spare column at the time each failure is detected. The order in which the spare rows and/or spare columns are allocated by the BISRA is referred to as a “repair strategy.” Although some of the known BISRA schemes and repair strategies are capable of performing repair functions for bit-oriented memories, they do not adequately support word-oriented memories. Moreover, the known BISRA schemes do not adequately handle multi-bit errors during at-speed testing of the memory.
One of the known BISRA schemes, known as the comprehensive real-time exhaustive search test and analysis (CRESTA) algorithm, simultaneously searches all possible repair strategies of a bit-oriented memory and processes each repair strategy in separate BISRA engines. See Kawagoe T. et al., “A Built-In Self-Repair Analyzer (CRESTA) for Embedded DRAMs,” Proc. IEEE Int'l Test Conference 2000, pp. 567–574 (2000). The CRESTA method relies on using multiple BISRA engines to serially repair defects as they are encountered in accordance with a BISRA engine's respective repair strategy. For example, if a memory has two spare rows and two spare columns, six repair strategies are analyzed using six BISRAs: RRCC, RCRC, RCCR, CRRC, CRCR, and CCRR, where C and R represent a spare column and a spare row, respectively. In general, the total number of possible spare-resource orderings is given by:
                                                        (                              m                +                n                            )                        !                                              m              !                        ⁢                          n              !                                      ,                            (        1        )            wherein m is the number of spare rows available and n is the number of spare columns available. Thus, for the example above where m=2 and n=2, the total number of possible spare-resource orderings is six. The total number of possible spare-resource orderings is sometimes referred to herein using the notation “C(m+n, m).”
The CRESTA method uses C(m+n, m) sub-analyzers to analyze the incoming row/column address information of faulty memory cells and to allocate the available repair resources according to all possible repair strategies. For example, a sub-analyzer using the repair strategy RRCC will allocate a spare row to the first faulty cell discovered, allocate another spare row to the next faulty cell discovered if the cell is not in the same row as the first faulty cell, allocate a spare column to the next faulty cell that is not in any faulty row already discovered, and finally allocate the second spare column to the next-discovered faulty cell that is neither in any faulty row already discovered nor in the same column as the memory cell repaired by the first spare column. If at least one of the sub-analyzers finds a successful repair strategy for repairing defects in memory, the chip is deemed repairable; otherwise, the chip is deemed unrepairable.
In the CRESTA method, each sub-analyzer stores the row address or the column address of a faulty memory cell whenever a respective spare row or spare column is allocated. When the next faulty memory cell is discovered, the stored addresses are checked to determine whether the memory cell can be repaired by a previously allocated spare resource. Consequently, the CRESTA method is unable to adequately handle at-speed multiple-bit failure analysis occurring in word-oriented memories. In particular, the CRESTA method cannot determine the number of spare columns needed for all failure bits in a word during a single clock cycle. Instead, in order to detect multi-bit errors, the CRESTA method must be paused or stopped. Some memory faults, however, are timing critical and cannot be detected if the BIST process is paused or stopped. Thus, a BISRA scheme that does not operate at-speed can miss critical errors in the memory and produce incomplete test results. Moreover, the time required to perform a self-test is not trivial.
Moreover, as more spare rows and columns are made available on an IC, the number of sub-analyzers required to implement the CRESTA method rises exponentially. At some point, the chip area used by sub-analyzers and spare memory resources will cost more than accepting the lower yields of ICs built without spare resources.
Accordingly, there is a need for an improved built-in self-repair analyzer scheme. Although not required, such an improved system can be used, for example, to detect and analyze multi-bit failures of a word-oriented memory and can also be used at the operating speed of the memory. Operating at-speed can not only detect faults in the memory that are undetectable using conventional schemes, but can significantly reduce the time required for testing.